Efficient hardware implementations of high throughput SHA-3 candidates keccak, luffa and blue midnight wish for single- and multi-message hashing

In November 2007 NIST announced that it would organize the SHA-3 competition to select a new cryptographic hash function family by 2012. In the selection process, hardware performances of the candidates will play an important role. Our analysis of previously proposed hardware implementations shows that three SHA-3 candidate algorithms can provide superior performance in hardware: Keccak, Luffa and Blue Midnight Wish (BMW). In this paper, we provide efficient and fast hardware implementations of these three algorithms. Considering both single- and multi-message hashing applications with an emphasis on both speed and efficiency, our work presents more comprehensive analysis of their hardware performances by providing different performance figures for different target devices. To our best knowledge, this is the first work that provides a comparative analysis of SHA-3 candidates in multi-message applications. We discover that BMW algorithm can provide much higher throughput than previously reported if used in multi-message hashing. We also show that better utilization of resources can increase speed via different configurations. We implement our designs using Verilog HDL, and map to both ASIC and FPGA devices (Spartan3, Virtex2, and Virtex 4) to give a better comparison with those in the literature. We report total area, maximum frequency, maximum throughput and throughput/area of the designs for all target devices. Given that the selection process for SHA3 is still open; our results will be instrumental to evaluate the hardware performance of the candidates

A baseline h.264 video encoder hardware design

The recently developed H.264 / MPEG-4 Part 10 video compression standard achieves better video compression efficiency than previous video compression standards at the expense of increased computational complexity and power consumption. Multiple reference frame (MRF) Motion Estimation (ME) is the most computationally intensive and power consuming part of H.264 video encoders. Therefore, in this thesis, we designed and implemented a reconfigurable baseline H.264 video encoder hardware for real-time portable applications in which the number of reference frames used for MRF ME can be configured based on the application requirements in order to trade-off video coding efficiency and power consumption. The proposed H.264 video encoder hardware is based on an existing low cost H.264 intra frame coder hardware and it includes new reconfigurable MRF ME, mode decision and motion compensation hardware. We first proposed a low complexity H.264 MRF ME algorithm and a low energy adaptive hardware for its real-time implementation. The proposed MRF ME algorithm reduces the computational complexity of MRF ME by using a dynamically determined number of reference frames for each Macroblock and early termination. The proposed MRF ME hardware architecture is implemented in Verilog HDL and mapped to a Xilinx Spartan 6 FPGA. The FPGA implementation is verified with post place & route simulations. The proposed H.264 MRF ME hardware has 29-72% less energy consumption on this FPGA than an H.264 MRF ME hardware using 5 reference frames for all MBs with a negligible PSNR loss. We then designed the H.264 video encoder hardware and implemented it in Verilog HDL. The proposed video encoder hardware is mapped to a Xilinx Virtex 6 FPGA and verified with post place & route simulations. The bitstream generated by the proposed video encoder hardware for an input frame is successfully decoded by H.264 Joint Model reference software decoder and the decoded frame is displayed using a YUV Player tool for visual verification. The FPGA implementation of the proposed H.264 video encoder hardware works at 135 MHz, it can code 55 CIF (352x288) frames per second, and its power consumption ranges between 115mW and 235mW depending on the number of reference frames used for MRF ME

Efficacy of custom-made soft keratoconus lenses on corneal aberrations and photic phenomena in patients with keratoconus: a corneal topography imaging based study

AIM: To evaluate the efficacy of custom-made soft keratoconus (KC) lenses on corneal aberrations and photic phenomena in two different optical zones in patients with KC. METHODS: Sixty eyes of 42 patients with KC were examined at baseline and after fitting HydroCone (Toris K) soft silicone hydrogel lenses. Best spectacle-corrected visual acuity (BSCVA) and contact lens-corrected visual acuity (CLCVA) were recorded. Lower- and higher-order corneal aberrations (LOAs and HOAs) were measured with and without Toris K lenses and compared in central 4.5 mm and 7 mm zones. Mesopic pupil diameter and subjective photic phenomena were also assessed. RESULTS: Mean CLCVA was significantly improved compared to BSCVA (P6.00 mm (85.7%). CONCLUSION: Toris K lenses provide good visual results and a significant reduction in central corneal aberrations in patients with KC but could cause an increase in peripheral aberrations. This practical and nonsurgical approach appears to be an effective method for the visual management of KC

A reconfigurable H.264 video encoder hardware (Bir uyarlanır H.264 video kodlayıcı donanımı)

Motion Estimation (ME) is the most computationally intensive part of video compression systems. Multiple reference frame (MRF) ME used in H.264 standard increases the video coding efficiency at the expense of increased computational complexity and power consumption. Therefore, in this paper, we present a reconfigurable baseline H.264 video encoder hardware in which the number of reference frames used for MRF ME can be configured based on the application requirements in order to trade-off video coding efficiency and power consumption. The proposed H.264 video encoder hardware is based on an existing low cost H.264 intra frame coder hardware and it includes new reconfigurable MRF ME, mode decision and motion compensation hardware. The proposed H.264 video encoder hardware is capable of processing 55 CIF (352×288) frames per second and its power consumption ranges between 115 mW and 235 mW depending on the number of reference frames used for MRF ME

A low power adaptive H.264 video encoder hardware

In this paper, we propose a low power adaptive baseline H.264 video encoder hardware for portable consumer electronics devices. Multiple reference frame motion estimation (MRF ME) used in H.264 standard increases the video coding efficiency at the expense of increased computational complexity and power consumption. In the proposed hardware, the number of reference frames used for MRF ME can be dynamically changed for each macroblock in order to trade-off video coding efficiency and power consumption. The proposed hardware can code 55 CIF (352x288) frames per second with low hardware cost. Its power consumption ranges between 115mW and 235mW depending on the number of reference frames used for MRF ME

A low energy adaptive hardware for H.264 multiple reference frame motion estimation

Multiple reference frame motion estimation (MRF ME) increases the video coding efficiency at the expense of increased computational complexity and energy consumption. Therefore, in this paper, a low complexity H.264 MRF ME algorithm and a low energy adaptive hardware for its real-time implementation are proposed. The proposed MRF ME algorithm reduces the computational complexity of MRF ME by using a dynamically determined number of reference frames for each Macroblock (MB) and early termination. The proposed H.264 MRF ME hardware is implemented in Verilog HDL. The proposed H.264 MRF ME hardware has 29-72% less energy consumption than an H.264 MRF ME hardware using 5 reference frames for all MBs with a negligible PSNR loss. Therefore, it can be used in consumer electronics products that require real-time video processing or compression with low power consumption

Tekin Acar Cosmetics

Ankara : İhsan Doğramacı Bilkent Üniversitesi İktisadi, İdari ve Sosyal Bilimler Fakültesi, Tarih Bölümü, 2015.This work is a student project of the The Department of History, Faculty of Economics, Administrative and Social Sciences, İhsan Doğramacı Bilkent University.by Özer, Abdürrahim

Scalable wi-fi intrusion detection for IoT systems

The pervasive and resource-constrained nature of Internet of Things (IoT) devices makes them attractive to be targeted by different means of cyber threats. There are a vast amount of botnets being deployed every day that aim to increase their presence on the Internet for realizing malicious activities with the help of the compromised interconnected devices. Therefore, monitoring IoT networks using intrusion detection systems is one of the major countermeasures against such threats. In this work, we present a machine learning based Wi-Fi intrusion detection system developed specifically for IoT devices. We show that a single multi-class classifier, which operates on the encrypted data collected from the wireless data link layer, is able to detect the benign traffic and six types of IoT attacks with an overall accuracy of 96.85%. Our model is a scalable one since there is no need to train different classifiers for different IoT devices. We also present an alternative attack classifier that outperforms the attack classification model which has been developed in an existing study using the same dataset